This invention relates, in general, to high speed digital testing systems and, more specifically, to the testing of high speed very large scale integrated circuit chips.
The testing of very high speed digital systems, such as VHSIC systems and other high speed very large scale integrated circuit (VLSIC) chips, can significantly affect the total manufacturing time of the device or circuit. Since these circuits usually have a large number of input and output lines or parallel bit positions, a particular output signal or bit pattern is produced for a specific input signal or bit pattern. By testing all of the possible output signal combinations, it can be determined whether the device under test is operating properly. If some of the output combinations fail the test, a determination can be made whether to declare the device defective or relegate it to a less severe service, a lower operating speed, or other operating conditions which do not require every output to be correct at the normal operating speed.
The test requirements can be met, in principle, by the use of conventional digital electronic technology. However, problems with such technology arise because of the need for large capacity, high speed memory and shift registers (-100 MHz), the degree of achievable parallelism, the expandability to very high clock frequencies (.gtoreq.500 MHz), and cost.
Present day very large scale integrated circuit chips often have up to 32 parallel input lines and 32 parallel outputs. To test such chips for every conceivable combination of inputs and outputs is an inordinate task and requires a considerable amount of time. Therefore, it is practical in many situations to test the circuit with a predetermined pattern or set of input signals which, in most cases, adequately determines whether the chip is satisfactory or is defective. It is also desirable to test the chip at its normal speed of operation, or clocking rate, to obtain a true indication of the performance of the chip under actual operating conditions. In addition, it is advantageous not only to detect the presence of errors in the output signal, but to indicate the location of the error and the state of the incorrect logic level detected.
Therefore, it is desirable, and it is an object of this invention, to provide a system and method for quickly and accurately testing high speed logic systems, and for giving location and state information about any detected errors.